1. Field of the Invention
The present invention relates to a method, system, and program for testing a bus interface.
2. Description of the Related Art
The Peripheral Component Interconnect (PCI) bus architecture provides a low latency path through which devices implementing the PCI architecture can communicate. Details of the PCI bus architecture are described in the publication xe2x80x9cPCI Local Bus Specification,xe2x80x9d Revisions 2.2 (Dec. 1998), published by the PCI Special Interest Group, which publication is incorporated herein by reference in its entirety. Each PCI device that communicates on the PCI bus includes a configuration space including information used to address the device on the PCI bus. During initialization, a device designated as the master processor accesses the PCI bus to detect all the PCI devices present on the PCI bus, builds a consistent address map, and then writes the PCI device base addresses to the configuration space registers of each PCI device. The base address registers define the addresses that other PCI devices on the PCI bus use to communicate with the PCI device to which the addresses are assigned. The base register addresses map into the Input/Output (I/O) space of the device as well as the memory space.
As part of a power-on self test (POST) during initialization, the master processor will test the PCI devices by reading and writing data to the assigned base addresses in the PCI devices to determine whether the read/write operations complete successfully. During the POST initialization, the master processor also tests the memory and registers of the PCI interface used by the master processor. Prior art PCI devices provide a separate bus interface between the master processor and the memory elements of the PCI interface used by the master processor that is separate from the PCI interface. For instance, in the prior art, the master processor may be embedded in a PCI card including memory and registers and the PCI bus interface would include a separate non-PCI bus interface on the card between the processor and the memory elements on the PCI card. Additionally, the master processor may be implemented in an Application Specific Integrated Circuit (ASIC) that includes the PCI interface and PCI memory and registers. During initialization, the master processor would use the non-PCI bus interface on the PCI card to test the memory and registers of the PCI interface used by the master processor. After the master processor verifies the accessibility of the base addresses assigned to the external PCI devices as well as the internal memory elements on the PCI card used by the master processor for PCI communication, the master processor would continue with initialization.
The above prior art initialization architecture requires the use of an additional non-PCI bus interface to test the memory registers of the master processor PCI interface. Further, because an internal interface is used to test the memory elements of the master processor PCI interface, the pins and other PCI interface circuitry between the PCI bus and the master processor PCI interface are not tested because the master processor tests the PCI interface memory elements on the internal non-PCI bus interface.
For these reasons, there is a need in the art for improved techniques for initializing a PCI or other type of bus interface device.
Provided are a method, system, and program for performing initialization operations in a system including a bus, bus interface and at least one bus device communicating on the bus. The bus interface includes memory capable of being accessed over the bus by the at least one bus device. All bus devices capable of communicating on the bus are detected and each detected bus device and bus interface is configured with base addresses that enable transmission of Input/Output (I/O) requests over the bus to the memory in the bus interface and memory in any bus device including memory accessible over the bus. Testing is performed on the base addresses of the memory in each bus device including memory accessible over the bus by issuing I/O requests to the base addresses of the memory in each bus device. Memory in the bus interface is tested by issuing I/O requests to the base addresses of the memory in the bus interface over the bus.
In further implementations, the bus interface includes an initiator and target, and the memory in the bus interface is accessible through the target. Testing the memory in the bus interface further comprises transmitting the I/O requests to the initiator. The I/O requests are transmitted to the bus and the target accesses the I/O requests placed on the bus by the initiator and performs the requested I/O requests. The I/O requests testing the memory on the bus interface test circuitry connecting the target and the bus.
Still further, the I/O requests to the memory of the bus interface comprise internal wrap signals between the initiator and target on the bus interface.
The bus interface, bus, and bus devices may implement the Peripheral Component Interconnect (PCI) architecture.
In still further implementations, the bus interface comprises a bridge between a primary bus and secondary bus. In such case, detecting and configuring all the bus devices comprises detecting and configuring all the bus devices capable of communicating on the primary bus and the secondary bus.
Further provided are a method, system, and program for performing a verification of a bus interface including an embedded device and memory. The bus interface enables communication with a bus. The bus interface memory is capable of being accessed by one bus device communicating over the bus and the embedded device uses the bus interface to communicate on the bus. The bus device tests the memory in the bus interface by issuing Input/Output (I/O) requests to the memory in the bus interface over the bus. The embedded device tests the memory in the bus interface by issuing Input/Output (I/O) requests to the memory in the bus interface over the bus, whereby the tests performed by the bus device and embedded device test whether the bus interface is capable of handling requests from multiple bus devices over the bus.
Described implementations provide a technique for testing the operability of memory devices within a bus interface using I/O requests transmitted using the lines connecting the bus and bus interface.